Immense progress has been made in the field of semiconductor production techniques by steadily reducing the critical dimensions of circuit elements, such as transistors, in highly complex integrated circuits. For example, critical dimensions of 30 nm or less have been implemented in highly complex logic circuitry and memory devices, thereby achieving high integration and packing density. Consequently, more and more functions may be integrated into a single integrated circuit die, thereby providing the possibility of forming entire systems on a semiconductor substrate of the integrated circuit die so that highly complex electronic circuits may be formed on the basis of a common manufacturing process (such as were plural integrated circuit dice are fabricated on a semiconductor wafer and subsequently diced apart).
Typically, upon increasing the complexity of an integrated circuit provided on a single integrated circuit die, the input/output (IO) capabilities also are increased in order to address the demands for communication with peripheral circuits in complex electronic systems. Typically, an integrated circuit die is coupled to an appropriate support substrate, for example, a lead frame, with the assembly then being encapsulated within a container or package to provide a packaged integrated circuit device. The package may impart superior thermal and mechanical integrity to the integrated circuit die and which may also present an appropriate interface so as to provide an electrical coupling from the package containing the integrated circuit die to a peripheral electronic component, such as a printed circuit board (PCB), which in turn may have any appropriate configuration so as to represent a part of an overall complex electronic system. Frequently used contact technologies for coupling the integrated circuit die within a package include wire bonding or direct electrical coupling of appropriately designed contact structures provided on the integrated circuit die and the support substrate for the package. For example, in the case of direct contact, solder balls, solder bumps, contact pads, or any other appropriate contact elements in the form of metal pillars and the like may be provided in appropriate metallization systems of the integrated circuit die in order to establish a reliable electrical and mechanical coupling upon attachment to the support substrate.
Although the packing density of complex integrated circuits has been significantly increased due to the reduction of the critical dimensions, as discussed above, the volumetric packing density of the device packages has not been increased in a similar proportion, since for higher complexity of the integrated circuits, in which basically a two dimensional complex arrangement of circuit elements is provided, a corresponding highly complex routing system is used in the package so as to finally appropriately couple to a PCB in order to combine the various components of a complex electronic system. To increase the volumetric packing density of an integrated circuit package, it has been proposed to provide three-dimensional (3D) die systems, in which two or more integrated circuit dies are provided in a stacked configuration within a single package, thereby significantly increasing the volumetric packing density for a given dimension of the package.
The three-dimensional assembly of the integrated circuit dies, however, may require appropriate routing strategies in order to establish electric communication between the individual electronic circuits provided in the various integrated circuit dies. Furthermore, generally the complexity of the routing arrangement in the package may also increase in order to provide the required input/output capabilities for coupling the package to other components, such as other packages and external electronic components of the electronic system under consideration. Typically the configuration of the contact structure of the integrated circuit dies, which are designed for a three-dimensional package configuration, may also significantly affect the entire design of each integrated circuit die as well as any related processes, such as the electrical test of individual integrated circuit dies. Furthermore, overall functionality of integrated circuit dies may depend on the characteristics of a three-dimensional package configuration, since, for instance, generally an increased length of electrical couplings may affect the high frequency behavior of complex systems, while also the thermal and mechanical constraints may have an influence on the finally obtained performance characteristics of a three-dimensional electronic system.
As shown in FIG. 1a, integrated circuits (IC) 102a, . . . , 102d are typically formed on a semiconductor wafer 101, such as a silicon wafer, or any other appropriate carrier material. Each of the ICs 102a, . . . , 102d may include at least one electronic circuit, such as complex digital circuitry, possibly in combination with memory areas, analog circuitry, power circuitry, or any combination and the like. An individual portion 102 of the wafer 101 may include a plurality of integrated circuits 102a, . . . , 102d, each of which forming an integrated circuit die after the wafer 101 has been diced. The ICs are provided in array form on the wafer 101 with appropriately dimensioned scribe lines 104 separating the individual ICs 102 from each other and defining the location where the dicing operation is performed to separate the ICs in to a plurality of integrated circuit dies. Each integrated circuit is enclosed by a metal region 103, usually referred to as seal ring or guard ring. The seal ring may provide for mechanical integrity during the separation of the wafer 101 by dicing. The scribe lines 104 may include appropriate test structures 105, which may be used for controlling and monitoring the overall process quality of the various manufacturing processes involved. Consequently, at a final stage of processing the integrated circuits ICs disposed on a wafer, electrical tests may be performed by using the test structures 105 (TEG: Test Element Group) provided in the scribe lines 104 and also electrical tests may be performed with the individual integrated circuits prior to separating the wafer 101 into individual integrated circuit dies.
As a consequence, the integrated circuits 102 are designed so as to achieve the required functionality in combination with a high die-internal integration density, thereby reducing the overall dimension of the integrated circuit die and allowing the fabrication of an increased number of integrated circuits on a single integrated circuit die. Furthermore, the design and manufacturing flow for fabricating the integrated circuits 102 on the wafer 101 are optimized such that the final electrical tests on a wafer basis may be performed with a desired high efficiency and fault coverage prior to incorporating the individual integrated circuit dies into an appropriate package to form a packaged integrated circuit device.
As is well-known, a general electronic system is coupled to the outside world by means of couplings/wired channels, such as cables or wires, optical fibers, etc., or by means of wireless channels of an electromagnetic type. Such couplings allow for exchanging information signals and/or supplying power/energy.
At the lowest level of an electronic system, couplings of circuit elements within a single integrated circuit die are established by providing conductive lines and an appropriate metallization system including vertical couplings or vias and horizontal metal lines, wherein in complex integrated circuits a plurality of metallization layers are stacked in order to provide the required electrical couplings between the individual circuit elements formed in an underlying semiconductor substrate. The intercoupling of different integrated circuit dies and of integrated circuit dies within a package is typically accomplished by providing appropriately dimensioned and positioned contact pads, for instance, at the last the metallization layer of the metallization system of a semiconductor device. Hence, such contact pads represent terminals or interfaces, which may couple to any other electronic components, such as a package support substrate, on the one hand, and may couple to metal lines and vias of the metallization system so as to finally couple to the individual circuit elements according to the required circuit layout.
The electrical coupling between a contact pad of the device and a system component may be implemented by wire bonding or bumps, i.e., protruding conductive elements used for contact, which are directly coupled to the pad.
In the case of the SiPs (System in package), extremely complex configurations may arise due to the complexity of the electrical couplings of the various parts, i.e., ICs dies, passive components, PCB, etc., of the system. Consequently, great efforts are being made for obtaining a compact contact structure in order to reduce the overall size of packages that may include one or more individual integrated circuit dies.
For example, U.S. Pat. No. 6,815,254, which is incorporated by reference, refers to the general issue of packaging complex semiconductor devices. In this document it is considered an important problem that packages of semiconductor devices generally allow access to the internal integrated circuit die only from a bottom side of the package. In particular when providing stacked integrated circuit dies in a package, appropriately designed contact structures are provided. Furthermore, due to the sophisticated manufacturing techniques and test procedures performed on a wafer basis, generally high-production yield may be obtained, wherein, however, upon packaging two or more semiconductor chips into a single package, any rework or modification of the packaged integrated circuit die is typically not possible, thereby increasing the probability of obtaining reduced production yield in a very late stage of the overall fabrication process.
In order to address the above identified problems, it is suggested in this U.S. Pat. No. 6,815,254 to provide a package assembly that includes an intervening package that may be coupled to a first package from a first substrate on the first side of the package and may be coupled to a second package from a second substrate on a second opposing side of the package. The electrical contact from one side of the intervening package to the other side may be established by bypassing the semiconductor die. That is, an appropriate contact structure is provided within the package that allows electrical coupling between two opposite sides of the semiconductor package without contacting the semiconductor die.
Although this concept may provide for superior coupling within the integrated circuit package, it appears, however, that the coupling is only enhanced in the vertical direction at the cost of horizontally increasing the dimensions of the first and second substrates in order to allow wire bonding for coupling the integrated circuit die within the package to a package substrate and to accommodate the additional vertical couplings, which provide for the direct electrical coupling between the first and second substrates without contacting the integrated circuit die. Furthermore, a further area may be required for the routing within the first and second substrates.
U.S. Pat. No. 7,923,290, which is incorporated by reference, relates to manufacturing techniques that address the demands for increased miniaturization of components, greater packaging density of integrated circuits, superior performance, and reduced costs for complex electronic devices, in particular with respect to portable information and communication devices, such as cellular phones, personal data assistants (PDAs), camcorders, notebook computers, and the like. As stated in U.S. Pat. No. 7,923,290, new solutions may be required with respect to conventional semiconductor packages, in which a semiconductor die is molded into a package with resin, wherein numerous package approaches have been proposed, such as a stacked configuration of multiple integrated circuit die, package in package (PIP), stacked package configurations, or package on package (POP), or any combinations thereof.
Basically, U.S. Pat. No. 7,923,290 proposes a solution in which an integrated-circuit packaging system is formed by providing a pre-formed interposer with a through-hole via above an integrated circuit die and a support structure in order to couple the integrated circuit die with a substrate positioned below the integrated circuit die and with a further package provided above the interposer. On the other hand, the additional support structure provides for direct contact between the bottom substrate and the additional package without requiring direct contact of the integrated circuit die. This is a configuration of the type PoP (Package on Package) and, thus, the area occupied by the package is dominated by the die with the largest dimensions. The presence of the support structure increases the dimensions of the package. Moreover, in this concept all intercouplings are finally rooted to the bottom surface of the lower package for being coupled to a PCB. Furthermore, the routing within the integrated circuit die is implemented on the basis of a TSV (through-silicon via or through substrate via) approach of the “via last” type, which, thus, requires the formation of the vias through the entire IC.
U.S. Pat. No. 5,646,446, which is incorporated by reference, aims at improving density in packaging so as to allow full performance potential of intercoupled integrated circuit dies. As stated in this document, typical integrated-circuit packages may contain only one die, wherein the package is substantially larger than the die, thereby significantly restricting the overall packaging density. These conventional packaging systems based on a printed circuit board with single die packages are inappropriate to provide a desired high number of dies within a volume and weight compatible with the demands of advanced circuit applications. In order to address these problems, it is suggested in this document to provide a three-dimensional flexible assembly of integrated circuits, wherein a folded flexible substrate with integrated circuit dies is provided. According to the proposed solution, mechanically and electrically functional attachment of integrated-circuit dies to one or both sides of the flexible substrates is accomplished by using a flip chip technique.
Hence, in this approach, a flexible printed circuit is used for coupling the various ICs in a vertically stacked configuration. Moreover, in this approach, all intercouplings are finally routed to the bottom surface of the package for being coupled to a PCB.
In United State Patent Application Publication No. 2010/0187676, which is incorporated by reference, the problem of reduced coupling in semiconductor packages is addressed by providing a cube semiconductor package. The package includes a semiconductor-die module including a semiconductor die having a first surface, a second surface opposite to the first surface, and side surfaces, wherein bond pads are placed on the first surface, and through-electrodes are provided, which pass through the first and second surfaces. Moreover, redistribution lines are placed at least on the first and/or second surface and are electrically coupled with the through-electrodes and the bond pads. End portions of the redistribution lines are flush with the side surfaces.
Furthermore, coupling members, such as solder bumps, are placed on the side surfaces and are electrically coupled with the ends of the redistribution lines. In United State Patent Application Publication No. 2010/0187676 are described, with reference to FIGS. 1 to 4, various examples of a cube semiconductor package, in which a side surface of the semiconductor die is used as a contact area coupled to the chip internal circuit elements by the redistribution lines, which in turn are formed on an insulation layer that is provided on a top surface of the semiconductor die. In some examples as described with reference to FIGS. 1 and 2, the solder bumps at the side surface turn out to be very small due to the thickness of the metal of the redistribution lines. In addition, the semiconductor diep is separated from the wafer, as also discussed above, so that typically a non-perfect side surface is generated during the dicing of the wafer, thereby also restricting the degree of alignment of the solder bump formed on the side surface. That is, the solder bumps formed on the side surface may not be appropriately aligned with each other. It is, therefore, very difficult to assemble and laterally couple two ICs lying on the same plane, and such a coupling turns out to be barely reliable, and may carry low levels of current.
Furthermore, the through-electrodes are made of a conducting material and extend through the integrated circuit die, without addressing the problem of an insulation between the through-electrodes and the semiconductor substrate of the integrated circuit die, which is generally conductive with a resistivity of fractions of ohm*cm or more. Therefore, the through-electrodes may form short-circuits or leakage paths to the semiconductor substrate of the integrated circuit die.
In other embodiments described in United State Patent Application Publication No. 2010/0187676 with reference to FIGS. 3 and 4, the contact area between the solder bumps and the redistribution lines at the side surface may be enhanced by providing extension parts of the redistribution lines. That is, the extension parts are provided on the side surface of the integrated circuit die in order to increase the dimensions of the contact area between the solder bump and the metal of the redistribution layer. However, no electrical insulation between the extension part and the side surface of the integrated circuit die is provided. It appears that the insulation layer is only present on top of the surface of the integrated circuit die.
As known, the wafer may have test structures (TEG) in the scribe lines, as discussed above with reference to FIG. 1a of the present patent application. For this purpose, some metal regions may be exposed laterally at the integrated circuit die after the dicing of the wafer. Consequently, such laterally exposed metal regions may come into contact with the extension parts, thereby possibly forming short-circuits and/or leakage paths.
Furthermore, such test structures (TEG) are typically formed on the semiconductor substrate of the integrated circuit die, which, as said before, is usually conducting and is usually grounded.
Consequently, since a proper lateral insulation between the extension parts and the side surface of the integrated circuit die is lacking, the system is unreliable and short circuits may arise with the substrate or leakage paths may form with the semiconductor substrate or other circuits (portions of TEGs circuits) or between the different extension parts. Therefore, the system may not work correctly, or may exhibit reduced reliability. Moreover, any technical advice as to how the extension parts could be formed on the side surface is not provided in United State Patent Application Publication No. 2010/0187676. Hence, also coupling between an integrated circuit die and a package extended to the side surface of the integrated circuit die, the solution proposed in United State Patent Application Publication No. 2010/0187676 may result in reduced reliability.
Furthermore, in very complex electronic systems including a plurality of packages, each of which may include one or more integrated circuit dies, the couplings of the various packages are distributed in the horizontal direction due to the required routing layout for the various components on one PCB. The various PCBs are then coupled to each other.
FIG. 1b schematically illustrates a cross-sectional view of an electronic system 100, in which integrated circuit dies 102a, 102b and 102c are disposed in corresponding packages 110a, 110b, 110c, wherein coupling of the integrated circuit dies with the corresponding packages is established by means of a corresponding contact structure 106a, 106b, 106c, which is shown in the form of a direct coupling, while in other cases, alternatively or additionally a wire-bond contact structure may be provided. On the other hand, the various packages communicate with a respective PCB, such as PCBs 130a, 130b by means of the corresponding package substrates 111a, 111b, 111c in combination with a corresponding contact structure 112a, 112b, 112c. As discussed above, in the corresponding PCBs, appropriate horizontal wiring networks, which are generally indicated as 131a, 131b, are provided so as to couple the various components of the electronic system 100. In the example shown, the PCB 130b provides the wiring network 131b so as to appropriately couple to the packages 110b, 110c. On the other hand, the PCB 130a provides the lateral routing so as to couple to the package 110a. Furthermore, both PCBs 130a, 130b additionally include horizontal routing resources so as to couple to a vertical coupling 132, which is configured enable the coupling of the individual PCBs 130a, 130b. 
Increasing the number of integrated circuit dies in the package helps to reduce the dimension of the whole system. However, the support substrate of the package couples the various ICs in the package to the other system components external to the package. This makes the routing extremely complicated, which often requires increasing the number of layers of the PCB and of the package substrate besides requiring an increase of the area occupied by the package substrate.
FIG. 1c schematically illustrates a cross-sectional view of the electronic system, wherein the package 110a includes two integrated circuit dies, thereby requiring a more complex contact structure 106 a so as to couple to the package substrate. Furthermore, the complexity of the contact structure 112a also increases, thereby also requiring a more complex horizontal wiring network 131a in the bottom PCB 130a. Although the overall size of the electronic system 100 in FIG. 1c may be reduced compared to the system 100 of FIG. 1b, increased complexity of the PCB 130a may render this solution less attractive.
Current packaging architectures are limited due to the fact that the coupling of the integrated circuit dies and the package develops in the vertical direction, and this often requires the routing between the various packages to increase in a substantially horizontal direction. Indeed, all intercouplings are brought to the bottom surface of the package for being coupled to a PCB and, when necessary, a part of intercouplings is also routed to the top surface for being coupled to an upper package (PoP).
Furthermore, for coupling the various PCBs, couplers and cables are used which increase the volume of the total system. Hence, with increasing complexity of the electronic system, the volume of the system may increase even in an over-proportional manner.
Also in the case of 3D integration in integrated circuit dies by means of TSV, the coupling of the various ICs is extended in a vertical direction.
FIG. 1d schematically illustrates a cross-sectional view of an electronic system 100, in which a plurality of integrated circuit dies 102a, 102b, 102c are directly coupled by forming a vertically arranged stack of integrated circuit dies, which may bonded to each other face to face or face to back or back to back, and the like. In the example shown, the integrated circuit die 102a includes a semiconductor substrate 108a, above which is provided an appropriate multilevel metallization system which is bonded to the integrated circuit die 102b, i.e., to the metallization system of the die, thereby establishing a face to face coupling. On the other hand, the substrate 108b of the integrated circuit die 102b includes an appropriate contact structure coupling to the metallization system and also to the bottom of the thinned semiconductor substrate 108b so as to couple to the metallization system of the integrated circuit die 102c, thereby implementing a face-to-back coupling. On the other hand, an appropriate contact structure on the basis of through-hole vias 106v may also be present at the back side of the thinned semiconductor substrate 108 of the integrated circuit die 102c, thereby enabling coupling to a corresponding package substrate.
Summarizing the above-described approaches that may be encountered in conventional electronic systems, it may be pointed out that generally, coupling in the packaging develops in a vertical direction, whereas in the PCBs the coupling increases in complexity in a horizontal direction, while in some cases the coupling provided on the basis of a side surface of an IC may suffer from reduced production yield and reliability.